Circuit Modeling – Basic Concepts, Functional Modeling at Logic and Register levels, Structural Models.
Logic Simulation – Simulation based Design Verification, Delay Models,
Gate-level Event Driven Simulation.
Fault Modeling – Logical Fault Models, Fault Detection, Equivalence and
Dominance, Single and Multiple Stuck-Fault Model.
Fault Simulation – General Fault Simulation Techniques, Fault Simulation
for Combinational Circuits, Fault Sampling.
Testing: Algorithms for Testing Single Stuck Fault and Bridge Faults,
Automatic Test Generation Concepts, Functional Testing, Random Test
Generators, Encoding techniques.
Design for Testability: Scan Based Design, Boundary Scan Techniques,
Compression Techniques, LFSRs, Built-in Self Test (BIST), BIST
Architectures and Advanced BIST Concepts.
Formal Verification : Model Checking, Equivalence Checking and
Theorem Proving, Design of tools for Formal Verification.
- Teacher: kama Kamakoti V
- Teacher: Gargi Mitra
- Teacher: CS12D024 PATANJALI S L P S K